High speed, density and reliability requirements for computer system applications of random access memory arrays, especially static random access memory (SRAM) arrays, require efficient and effective test applications to process and manufacture viable components for subsequent incorporation into high end processor products. Manufacturing yield, and, ultimately, product cost are integral parts of the ability to design, manufacture, and sell computer systems in the marketplace. A key requirement to achieving leading edge technology implementations is the ability to provide for effective testing and diagnostics in the design/manufacturing process to lower overall technology cost prior to product volume ramp-up.
Efficient SRAM/DRAM designs stress the manufacturing process capability. This is because of the high device usage (gates and transistor elements) in a given area (smaller memory cells yield a higher number of bits per chip), and high end processor applications demand high memory bit usage. The drive for high gate density chips with a large number of gates per unit area results in an increased sensitivity to process defects over the accompanying logic, and this, in turn, drives the need to analyze, understand, and eventually reduce overall process defect density to achieve product yield and cost requirements.
To this end, integrated self test, and particularly for the memory arrays, Array Built In Self Test (ABIST) has been employed to provide deterministic test coverage ensuring high quality products. Assessment of test effectiveness and diagnosis of fails to initial manufacturing test and subsequent stress screens are critical to yield diagnostics and product reliability improvement efforts, as they are more realistic indicators than monitor structures. Monitor structures are easier to diagnose, but are only models of the product/process interaction, and are expensive from the perspective of area overhead and process productivity.
Execution of ABIST algorithms requires either explicit test programming for micro-programmable architectures or state machine based algorithms. An ABIST that is synchronous to an external test system, where an off-chip fail indicator is monitored on a cycle-by-cycle basis determines at which points in the test the array fails.
In an ABIST, generation of memory/array addressing is accomplished with a single or plurality of sequential counters. These sequential counters comprise the address space of the memory under test and can be divided into appropriate sub-groups representing the row/column and or subarray dimensions of the memory array under test. Current technology provides for incrementing and decrementing the address through the address space of the memory array, and can alter the significance of the address groups i.e. Ripple row addressing as least significant, then column, or ripple column addressing as least significant, then row to accomplish the intended test sequences. Some systems even provide for maximum address programmability to restrict the count of a wide counter implementation in order to provide self test capability for a plurality of memory array macros that have varying address sizes (width or dimension).
Traditional ‘n’-sequence deterministic test only allows for test operations at individual memory cell locations to proceed along the address dimension set up as least significant, and a minimum of ‘n’ or a multiple of ‘n’ test cycles must pass before the target cell of an operation can be revisited to determine if it has been affected by preceding operations.
This process is adequate to provide n-sequential address testing of memory arrays, such as static memory arrays (SRAMs) utilizing clocked operations with memory cell recovery prior to subsequent operations. This is done through the use of counter control logic, and provisions for division of the address application rate to the memory array device under test (dut) can be made. This allows for multi-cycle per cell operations whereby a plurality of write or read (e.g. RxWxRx) operations at each addressed location can be accomplished.
Alternative test methodologies to comprehensively test each memory location transitioning to and from each memory location (cell), referred to as n2 addressing have been described in literature, and commonly used for characterization in the past, but are not widely used in clocked CMOS manufacturing test applications due to the prohibitively long test time and cost implications.
However, the capability to stress controlled address and address group transitions is becoming more important to test for long time constant effects and implement low level defect screens in a cost effective and flexible manner.